Process variations can cause component characteristics on a semiconductor die to greatly vary. In particular, with complementary components, such as n-channel and p-channel metal oxide semiconductor field effect transistors (MOSFETs), one component type may have a process variation such that one of the conductivity type components may be at a fast operation, while the other component may be at a slow operation. In yet another case, both conductivity type components may be a fast operation. Lastly, both conductivity type component may be at a slow operation.
In this way, a circuit designer must design circuitry to operate at all of the four corners (e.g. fast p-channel, fast n-channel: fast p-channel, slow n-channel, slow p-channel, fast n-channel: and slow p-channel, slow n-channel). Such variations must be compensated by designing circuitry to operate with an adequate margin. By doing so, circuitry may not be designed for optimal speed and/or power.
In view of the above, it would be desirable to provide a way of compensating for process variations such that circuits may be optimized for speed and/or power regardless as to where within the four corners of process variation the particular device may fall.